Category: JEDEC

Potential Failure Mode and Effects Analysis (FMEA)
standard by JEDEC Solid State Technology Association, 08/01/2018

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
standard by JEDEC Solid State Technology Association, 09/01/2004

IC LATCH-UP TEST
standard by JEDEC Solid State Technology Association, 11/01/2011

TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR DISCRETE SEMICONDUCTOR AND OPTOELECTRONIC DEVICES
standard by JEDEC Solid State Technology Association, 10/01/2009

METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESS
standard by JEDEC Solid State Technology Association, 03/01/2006

Low Power Double Data Rate 3 SDRAM (LPDDR3)
standard by JEDEC Solid State Technology Association, 08/01/2015

ADDENDUM No. 1 TO EIA-397
Amendment by JEDEC Solid State Technology Association, 07/01/1980

Inspection Criteria for Microelectronic Packages and Covers
standard by JEDEC Solid State Technology Association, 05/01/2011

Embedded Multi-media card (e*MMC), Electrical Standard (4.5 Device)
standard by JEDEC Solid State Technology Association, 06/01/2011

IC LATCH-UP TEST
standard by JEDEC Solid State Technology Association, 04/01/2016