Category: JEDEC

DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 10/01/2011

MULTIMEDIACARD (MMC) ELECTRICAL STANDARD, STANDARD CAPACITY (MMCA, 4.1)
standard by JEDEC Solid State Technology Association, 06/01/2007

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 02/01/2011

ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing – Human Body Modal (HBM) – Component Level
standard by JEDEC Solid State Technology Association, 05/12/2017

DDR4 REGISTER CLOCK DRIVER (DDR4RCD01)
standard by JEDEC Solid State Technology Association, 08/01/2016

3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions
standard by JEDEC Solid State Technology Association, 11/01/2009

Universal Flash Storage (UFS) Unified Memory Extention
standard by JEDEC Solid State Technology Association, 03/01/2016

Embedded Multi-media card (e*MMC), Electrical Standard 4.51
standard by JEDEC Solid State Technology Association, 06/01/2012

Addendum No. 1 to 3D Stacked SDRAM
Amendment by JEDEC Solid State Technology Association, 12/01/2013