Category: JEDEC

FOUNDRY PROCESS QUALIFICATION GUIDELINES – BACKEND OF LINE (Wafer Fabrication Manufacturing Sites)
standard by JEDEC Solid State Technology Association, 09/01/2018

Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilities
standard by JEDEC Solid State Technology Association, 12/01/2015

STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC
standard by JEDEC Solid State Technology Association, 01/01/1993

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION
standard by JEDEC Solid State Technology Association, 08/01/2008

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES
standard by JEDEC Solid State Technology Association, 03/01/2018

LOW POWER DOUBLE DATA RATE 2 (LPDDR2)
standard by JEDEC Solid State Technology Association, 02/01/2010

STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES
standard by JEDEC Solid State Technology Association, 09/01/1990

LIFE TEST METHODS FOR PHOTOCONDUCTIVE CELLS
standard by JEDEC Solid State Technology Association, 09/01/1969

UNDERSTANDING ELECTRICAL OVERSTRESS – EOS
standard by JEDEC Solid State Technology Association, 09/01/2016

Failure Mechanisms and Models for Semiconductor Devices
standard by JEDEC Solid State Technology Association, 09/01/2016