Category: JEDEC

DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007

HIgh Bandwidth Memory (HBM) DRAM
standard by JEDEC Solid State Technology Association, 11/01/2015

BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS
standard by JEDEC Solid State Technology Association, 03/01/2006

Graphics Double Data Rate (GDDR5) SGRAM Standard
standard by JEDEC Solid State Technology Association, 12/01/2013

EMBEDDED MULTIMEDIACARD (e*MMC) e*MMC/CARD PRODUCT STANDARD, HIGH CAPACITY, INCLUDING RELIABLE WRITE, BOOT, AND SLEEP MODES (MMCA, 4.3)
standard by JEDEC Solid State Technology Association, 12/01/2007

SELECTION OF BURN-IN/LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2015

Universal Flash Storage (UFS) Host Controller Interface
standard by JEDEC Solid State Technology Association, 08/01/2011

Test Standard for the Measurement of Proton Radiation Single Event Effects in Electronic Devices
standard by JEDEC Solid State Technology Association, 10/01/2013

Graphics Double Data Rate (GDDR6) SGRAM Standard
standard by JEDEC Solid State Technology Association, 07/01/2017

METAL PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES AND COVERS
standard by JEDEC Solid State Technology Association, 04/01/1987