JEDEC JESD47J.01
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2017
JEDEC
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2017
DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
standard by JEDEC Solid State Technology Association, 02/01/2008
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 10/01/2016
, Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices
standard by JEDEC Solid State Technology Association, 12/01/2015
STATISTICAL PROCESS CONTROL SYSTEMS
standard by JEDEC Solid State Technology Association, 04/01/2015
DDR4 NVDIMM-N Design Standard
standard by JEDEC Solid State Technology Association, 09/01/2016
POD135 – 1.35 V PSEUDO OPEN DRAIN I/O
standard by JEDEC Solid State Technology Association, 09/01/2013
Descriptive Designation System for Semiconductor-device Packages
standard by JEDEC Solid State Technology Association, 01/01/2016
JOINT IPC/JEDEC STANDARD FOR MOISTURE/REFLOW SENSITIVITY CLASSIFICATION FOR NONHERMETIC SOLID STATE SURFACE-MOUNT DEVICES
standard by JEDEC Solid State Technology Association, 03/01/2008
SOLDERABILITY
standard by JEDEC Solid State Technology Association, 10/01/2007