Category: JEDEC

Low Power Double Data Rate 5 (LPDDR5)
standard by JEDEC Solid State Technology Association, 02/01/2019

PROCEDURE FOR THE EVQLUQTION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY
standard by JEDEC Solid State Technology Association, 07/01/2015

Byte Addressable Energy Backed Interface
standard by JEDEC Solid State Technology Association, 09/01/2017

STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)
standard by JEDEC Solid State Technology Association, 09/01/2003

DDR4 SDRAM Standard
standard by JEDEC Solid State Technology Association, 06/01/2017

Embedded Multi-media card (e*MMC), Electrical Standard (5.01)
standard by JEDEC Solid State Technology Association, 07/01/2014

Addendum No. 1 to JESD79-4, 3D Stacked DRAM Standard
Amendment by JEDEC Solid State Technology Association, 02/01/2017

INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD – ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE)
standard by JEDEC Solid State Technology Association, 12/01/1995

UNIVERSAL FLASH STORAGE (UFS) SECURITY EXTENSION
standard by JEDEC Solid State Technology Association, 11/01/2016

ADDENDUM No. 9B to JESD8 – STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
standard by JEDEC Solid State Technology Association, 05/01/2002